Integrated circuits are becoming more densely packed with increasing numbers of individual circuit elements. Typically, testing these circuit elements is performed by generating a test pattern and applying the test pattern to the inputs of the integrated circuit using multiplexed, “mux,” scan flip-flops. Depending on the test pattern, the responses of the integrated circuit to the test pattern can provide an accurate indication of the existence or non-existence of defects.
A scan mode signal is sent to the integrated circuit to effect either a system mode or a test mode. In system mode, the integrated circuit functions according to its designed application. In test mode, the integrated circuit receives test patterns and performs other test operations. One such integrated circuit that is tested in a scan mode is a microprocessor.
The internal circuitry of a microprocessor is often separated into combinational blocks and sequential blocks, the sequential blocks comprising clocked circuitry such as flip-flops. A circuit used for testing combinational and sequential circuit blocks in a microprocessor is a “scan chain.” A scan chain includes a plurality of storage elements that are cascaded such that the output of a first storage element is coupled to the input of the next stage storage element. Scan chains thus allow testing of microprocessor circuit blocks by serially scanning in test patterns to the storage elements. The test patterns are then applied to the circuit blocks, and circuit test results are serially scanned out.